SPWM發(fā)生器VHDL正弦波脈寬調(diào)制頻率相位可調(diào)仿真

名稱(chēng)：SPWM發(fā)生器VHDL正弦波脈寬調(diào)制頻率相位可調(diào)仿真（代碼在文末下載）

軟件：Quartus II

語(yǔ)言：VHDL

代碼功能：

完成基于FPGA的SPWM發(fā)生器的設(shè)計(jì)，編寫(xiě)VHDL語(yǔ)言程序并調(diào)試，實(shí)現(xiàn)SPWM發(fā)生器的設(shè)計(jì)，可以輸出三路頻率和相位可調(diào)的SPWM信號(hào)。

實(shí)現(xiàn)的方法：分別產(chǎn)生正弦波和三角波，將正弦波和三角波進(jìn)行比較，得到SPWM波形

FPGA代碼Verilog/VHDL代碼資源下載：www.hdlcode.com

演示視頻：

設(shè)計(jì)文檔：

1. 工程文件

2. 程序文件

3. 程序編譯

4. RTL圖

5. 仿真圖

整體仿真圖

部分波形放大

相位累加器模塊

初相位調(diào)整模塊

部分代碼展示:

LIBRARY?ieee;
???USE?ieee.std_logic_1164.all;
???USE?ieee.std_logic_unsigned.all;
--三路spwm波
ENTITY?Sweep_frequency?IS
???PORT?(
??????clk??????????????:?IN?STD_LOGIC;--時(shí)鐘
??sin_freq_1?????????:?IN?STD_LOGIC_VECTOR?(9?DOWNTO?0);--頻率控制字1
??sin_freq_2?????????:?IN?STD_LOGIC_VECTOR?(9?DOWNTO?0);--頻率控制字2
??sin_freq_3?????????:?IN?STD_LOGIC_VECTOR?(9?DOWNTO?0);--頻率控制字3
??phase_1??????????:?IN?STD_LOGIC_VECTOR(9?DOWNTO?0);--相位控制字1
??phase_2??????????:?IN?STD_LOGIC_VECTOR(9?DOWNTO?0);--相位控制字2
??phase_3??????????:?IN?STD_LOGIC_VECTOR(9?DOWNTO?0);--相位控制字3
??????PWM_wave1????????:?OUT?STD_LOGIC;--輸出PWM波形1
??PWM_wave2????????:?OUT?STD_LOGIC;--輸出PWM波形2
??PWM_wave3????????:?OUT?STD_LOGIC?--輸出PWM波形3
???);
END?Sweep_frequency;
ARCHITECTURE?behavioral?OF?Sweep_frequency?IS
--sin?ROM表
COMPONENT?sin_ROM?IS
PORT
(
address:?IN?STD_LOGIC_VECTOR?(9?DOWNTO?0);
clock:?IN?STD_LOGIC??:=?'1';
q:?OUT?STD_LOGIC_VECTOR?(9?DOWNTO?0)
);
END?COMPONENT;
--三角波?ROM表
COMPONENT?triangle_ROM?IS
PORT
(
address:?IN?STD_LOGIC_VECTOR?(9?DOWNTO?0);
clock:?IN?STD_LOGIC??:=?'1';
q:?OUT?STD_LOGIC_VECTOR?(9?DOWNTO?0)
);
END?COMPONENT;
?--相位累加器
???COMPONENT?Freq_sum?IS
??????PORT?(
?????????clk?????????????:?IN?STD_LOGIC;
?????????freq_data???????:?IN?STD_LOGIC_VECTOR(9?DOWNTO?0);
?????????freq_out????????:?OUT?STD_LOGIC_VECTOR(9?DOWNTO?0)
??????);
???END?COMPONENT;
--初相位調(diào)整
COMPONENT?phase_crtl?IS
???PORT?(
??????clk?????????:?IN?STD_LOGIC;
??????freq_out????:?IN?STD_LOGIC_VECTOR(9?DOWNTO?0);--相位累加器輸出
??????phase_data??:?IN?STD_LOGIC_VECTOR(9?DOWNTO?0);--相位控制字10bit
??????address?????:?OUT?STD_LOGIC_VECTOR(9?DOWNTO?0)--查找表地址
???);
END?COMPONENT;
???
???SIGNAL?address_1??:?STD_LOGIC_VECTOR(9?DOWNTO?0);
SIGNAL?address_2??:?STD_LOGIC_VECTOR(9?DOWNTO?0);
SIGNAL?address_3??:?STD_LOGIC_VECTOR(9?DOWNTO?0);
SIGNAL?freq_out_sin_1??:?STD_LOGIC_VECTOR(9?DOWNTO?0);
SIGNAL?freq_out_sin_2??:?STD_LOGIC_VECTOR(9?DOWNTO?0);
SIGNAL?freq_out_sin_3??:?STD_LOGIC_VECTOR(9?DOWNTO?0);
???SIGNAL?q_sin1?????????:?STD_LOGIC_VECTOR(9?DOWNTO?0);--ROM輸出波形
SIGNAL?q_sin2?????????:?STD_LOGIC_VECTOR(9?DOWNTO?0);--ROM輸出波形
SIGNAL?q_sin3?????????:?STD_LOGIC_VECTOR(9?DOWNTO?0);--ROM輸出波形
???SIGNAL?freq_out_triangle??:?STD_LOGIC_VECTOR(9?DOWNTO?0);
???SIGNAL?q_triangle?????????:?STD_LOGIC_VECTOR(9?DOWNTO?0);--ROM輸出波形
BEGIN
???
???
???--sin存儲(chǔ)Rom表
???i1_sin_ROM?:?sin_ROM
??????PORT?MAP?(
?????????address??=>?address_1,--查找表地址
?????????clock????=>?clk,--時(shí)鐘
?????????q????????=>?q_sin1--輸出波形
??????);
???--sin存儲(chǔ)Rom表
???i2_sin_ROM?:?sin_ROM
??????PORT?MAP?(
?????????address??=>?address_2,--查找表地址
?????????clock????=>?clk,--時(shí)鐘
?????????q????????=>?q_sin2--輸出波形
??????);
???--sin存儲(chǔ)Rom表
???i3_sin_ROM?:?sin_ROM
??????PORT?MAP?(
?????????address??=>?address_3,--查找表地址
?????????clock????=>?clk,--時(shí)鐘
?????????q????????=>?q_sin3--輸出波形
??????);
???--triangle存儲(chǔ)Rom表
???i_triangle_ROM?:?triangle_ROM
??????PORT?MAP?(
?????????address??=>?freq_out_triangle,--查找表地址
?????????clock????=>?clk,--時(shí)鐘
?????????q????????=>?q_triangle--輸出波形
??????);
???
???--正弦波相位累加器--頻率控制
???i1_Freq_sum?:?Freq_sum
??????PORT?MAP?(
?????????clk????????=>?clk,
?????????freq_data??=>?sin_freq_1,--頻率控制字10bit----1
?????????freq_out???=>?freq_out_sin_1--累加器輸出
??????);
??
???--正弦波相位累加器--頻率控制
???i2_Freq_sum?:?Freq_sum
??????PORT?MAP?(
?????????clk????????=>?clk,
?????????freq_data??=>?sin_freq_2,--頻率控制字10bit----2
?????????freq_out???=>?freq_out_sin_2--累加器輸出
??????);
???--正弦波相位累加器--頻率控制
???i3_Freq_sum?:?Freq_sum
??????PORT?MAP?(
?????????clk????????=>?clk,
?????????freq_data??=>?sin_freq_3,--頻率控制字10bit----3
?????????freq_out???=>?freq_out_sin_3--累加器輸出
??????);
??
--初相位調(diào)整-0
i1_phase_crtl:?phase_crtl
???PORT?MAP(
??????clk?????????=>?clk,
??????freq_out????=>?freq_out_sin_1,--累加器輸出
??????phase_data??=>?phase_1,--相位控制字10bit---"0000000000"
??????address?????=>?address_1--查找表地址
???);
--初相位調(diào)整
i2_phase_crtl:?phase_crtl
???PORT?MAP(
??????clk?????????=>?clk,
??????freq_out????=>?freq_out_sin_2,--累加器輸出
??????phase_data??=>?phase_2,--相位控制字10bit--"0101010101"
??????address?????=>?address_2--查找表地址
???);
--初相位調(diào)整
i3_phase_crtl:?phase_crtl
???PORT?MAP(
??????clk?????????=>?clk,
??????freq_out????=>?freq_out_sin_3,--累加器輸出
??????phase_data??=>?phase_3,--相位控制字10bit--"1010101010"
??????address?????=>?address_3--查找表地址
???);
???--三角波相位累加器
???i4_Freq_sum?:?Freq_sum
??????PORT?MAP?(
?????????clk????????=>?clk,
?????????freq_data??=>?"0000100000",--頻率控制字10bit
?????????freq_out???=>?freq_out_triangle--累加器輸出
??????);
PWM_wave1<='1'?when?freq_out_triangle>q_sin1?else?'0';--三角波大于正弦波時(shí)輸出1，否則輸出0
PWM_wave2<='1'?when?freq_out_triangle>q_sin2?else?'0';--三角波大于正弦波時(shí)輸出1，否則輸出0
PWM_wave3<='1'?when?freq_out_triangle>q_sin3?else?'0';--三角波大于正弦波時(shí)輸出1，否則輸出0
END?behavioral;