8通道模數(shù)轉(zhuǎn)換AD7091驅(qū)動(dòng)代碼SPI接口12bitADC

名稱：8通道模數(shù)轉(zhuǎn)換AD7091驅(qū)動(dòng)代碼（代碼在文末付費(fèi)下載）

軟件：QuartusII

語言：Verilog

代碼功能：

使用verilog代碼設(shè)計(jì)AD7091R-8驅(qū)動(dòng)代碼。

控制接口為SPI接口，實(shí)現(xiàn)8通道模數(shù)轉(zhuǎn)換，輸出8通道數(shù)字信號。

FPGA代碼Verilog/VHDL代碼資源下載網(wǎng)：www.hdlcode.com

芯片手冊：

AD7091R-2_7091R-4_7091R-8.pdf

部分代碼展示

//AD7091驅(qū)動(dòng)
module?AD7091(
input?clk_50M,
//input?reset_p,
output?AD_CS,
output?AD_convst,
output?AD_sclk,//輸出sclk
input?AD_sdo,//輸入sdo
output?AD_sdi,//輸出sdi
input?AD_alert,
output?reg?[11:0]?AD_0,
output?reg?[11:0]?AD_1,
output?reg?[11:0]?AD_2,
output?reg?[11:0]?AD_3,
output?reg?[11:0]?AD_4,
output?reg?[11:0]?AD_5,
output?reg?[11:0]?AD_6,
output?reg?[11:0]?AD_7
);
wire?reset_p;
assign?reset_p=0;
reg?[2:0]?state=3'd0;
parameter?s_idle=3'd0;
parameter?s_initial=3'd1;
parameter?s_write=3'd2;
parameter?s_wait=3'd3;
reg?[7:0]?convst_cnt=8'd0;
reg?[7:0]?write_cnt=8'd0;
reg?[7:0]?wait_cnt=8'd0;
//狀態(tài)機(jī)
always@(posedge?clk_50M?or?posedge?reset_p)
if(reset_p)
state<=s_idle;
else
case(state)
s_idle:
state<=s_initial;
s_initial://初始化狀態(tài)
if(convst_cnt>=8'd66)
state<=s_wait;
else
state<=s_initial;
s_wait:
if(wait_cnt>=8'd200)
state<=s_write;
else
state<=s_wait;
s_write://讀寫狀態(tài)
state<=s_write;
default:;
endcase
always@(posedge?clk_50M?or?posedge?reset_p)
if(reset_p)
wait_cnt<=8'd0;
else
if(state==s_wait)
wait_cnt<=wait_cnt+8'd1;
else
wait_cnt<=8'd0;
//初始化計(jì)數(shù)400輸出66個(gè)convst周期
reg?[9:0]?clk_convst_cnt=10'd0;
always@(posedge?clk_50M?or?posedge?reset_p)
if(reset_p)
clk_convst_cnt<=10'd0;
else
if(state==s_initial)
if(clk_convst_cnt>=10'd400)
clk_convst_cnt<=10'd0;
else
clk_convst_cnt<=clk_convst_cnt+10'd1;
else
clk_convst_cnt<=10'd0;
reg?convst_initial=1;
always@(posedge?clk_50M?or?posedge?reset_p)
if(reset_p)
convst_initial<=1;
else
if(state==s_initial)
if(clk_convst_cnt>10'd200)//400us低電平，400us高電平
convst_initial<=0;
else
convst_initial<=1;
else
convst_initial<=1;
always@(posedge?clk_50M?or?posedge?reset_p)
if(reset_p)
convst_cnt<=8'd0;
else
if(state==s_initial)
if(clk_convst_cnt>=10'd400)
convst_cnt<=convst_cnt+8'd1;//convst計(jì)數(shù)
else
convst_cnt<=convst_cnt;
else
convst_cnt<=8'd0;