名稱:數(shù)字鐘設(shè)計VHDL代碼Quartus? 實驗箱
軟件:Quartus
語言:VHDL
代碼功能:數(shù)字鐘
FPGA代碼Verilog/VHDL代碼資源下載:www.hdlcode.com
本代碼已在實驗箱驗證,實驗箱如下,其他開發(fā)板可以修改管腳適配:
演示視頻:
設(shè)計文檔:
1、工程文件
2、程序文件
3、程序編譯
4、RTL圖
5、管腳分配
6、仿真圖
整體仿真圖
分頻模塊
計時模塊
顯示模塊
部分代碼展示:
LIBRARY?ieee; USE?ieee.std_logic_1164.all; USE?ieee.std_logic_unsigned.all; --?顯示模塊實體聲明 ENTITY?display?IS ???PORT?( ??????clk????????????????:?IN?STD_LOGIC;??????????????????????--?時鐘信號 ??????hour_time??????????:?IN?STD_LOGIC_VECTOR(7?DOWNTO?0);???--?小時時間輸入 ??????minute_time????????:?IN?STD_LOGIC_VECTOR(7?DOWNTO?0);???--?分鐘時間輸入 ??????second_time????????:?IN?STD_LOGIC_VECTOR(7?DOWNTO?0);???--?秒時間輸入 ??????bit_select?????????:?OUT?STD_LOGIC_VECTOR(5?DOWNTO?0);??--?位選擇輸出,用于選擇顯示的位數(shù) ??????seg_select?????????:?OUT?STD_LOGIC_VECTOR(7?DOWNTO?0)???--?段選擇輸出,用于選擇七段顯示器的段 ???); END?display; --?顯示模塊的行為描述 ARCHITECTURE?bahave?OF?display?IS --?BCD轉(zhuǎn)換組件聲明 COMPONENT?BCD?IS ???PORT?( ??????clk??????:?IN?STD_LOGIC; ??????binary???:?IN?STD_LOGIC_VECTOR(7?DOWNTO?0);????????????--?二進(jìn)制數(shù)輸入 ??????Tens?????:?OUT?STD_LOGIC_VECTOR(3?DOWNTO?0);???????????--?十位輸出 ??????Ones?????:?OUT?STD_LOGIC_VECTOR(3?DOWNTO?0)????????????--?個位輸出 ???); END?COMPONENT; --?信號聲明 SIGNAL?second_time_one?????:?STD_LOGIC_VECTOR(3?DOWNTO?0)?:=?"0000";?--?秒的個位 SIGNAL?second_time_ten?????:?STD_LOGIC_VECTOR(3?DOWNTO?0)?:=?"0000";?--?秒的十位 SIGNAL?minute_time_one?????:?STD_LOGIC_VECTOR(3?DOWNTO?0)?:=?"0000";?--?分的個位 SIGNAL?minute_time_ten?????:?STD_LOGIC_VECTOR(3?DOWNTO?0)?:=?"0000";?--?分的十位 SIGNAL?hour_time_one???????:?STD_LOGIC_VECTOR(3?DOWNTO?0)?:=?"0000";?--?小時的個位 SIGNAL?hour_time_ten???????:?STD_LOGIC_VECTOR(3?DOWNTO?0)?:=?"0000";?--?小時的十位 SIGNAL?display_num?????????:?STD_LOGIC_VECTOR(3?DOWNTO?0)?:=?"0000";?--?當(dāng)前顯示的數(shù)字 SIGNAL?select_bit??????????:?STD_LOGIC_VECTOR(15?DOWNTO?0)?:=?"0000000000000000";?--?位選擇計數(shù)器 SIGNAL?number??????????????:?STD_LOGIC_VECTOR(2?DOWNTO?0)?:=?"000";?--?數(shù)字選擇計數(shù)器 SIGNAL?time_count??????????:?STD_LOGIC_VECTOR(31?DOWNTO?0)?:=?"00000000000000000000000000000000";?--?未使用的信號 BEGIN --?將時間轉(zhuǎn)換為十位和個位 U1_BCD:?BCD ???PORT?MAP( ??????clk?????=>?clk, ??????binary??=>?second_time, ??????Tens????=>?second_time_ten, ??????Ones????=>?second_time_one ???); U2_BCD:?BCD ???PORT?MAP( ??????clk?????=>?clk, ??????binary??=>?minute_time, ??????Tens????=>?minute_time_ten, ??????Ones????=>?minute_time_one ???); U3_BCD:?BCD ???PORT?MAP( ??????clk?????=>?clk, ??????binary??=>?hour_time, ??????Tens????=>?hour_time_ten, ??????Ones????=>?hour_time_one ???); --?位選擇過程 PROCESS?(clk) BEGIN ???IF?(clk'EVENT?AND?clk?=?'1')?THEN ??????IF?(select_bit?=?"1111111111111111")?THEN?--?當(dāng)計數(shù)器達(dá)到8時重置 ?????????select_bit?<=?"0000000000000000"; ??????ELSE ?????????select_bit?<=?select_bit?+?"0000000000000001";?--?計數(shù)器加1 ??????END?IF; ???END?IF; END?PROCESS; --?數(shù)字選擇過程 PROCESS?(clk) BEGIN ???IF?(clk'EVENT?AND?clk?=?'1')?THEN ??????IF?(select_bit?=?"1111111111111111")?THEN ?????????IF?(number?=?"101")?THEN?--?當(dāng)數(shù)字達(dá)到5時重置 ????????????number?<=?"000"; ?????????ELSE ????????????number?<=?number?+?"001";?--?數(shù)字加1 ?????????END?IF; ??????END?IF; ???END?IF; END?PROCESS;
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